1. Field of the Invention
Embodiments of the present invention relate generally to integrated circuit sense amplifier design and more specifically to a process variation tolerant sense amplifier flop design.
2. Description of the Related Art
Integrated circuits frequently employ certain common system building block circuits, such as logic gates, memories blocks, and other specialty circuits to construct the overall system functionality of a given integrated circuit. Process variation associated with the manufacture of integrated circuits generally imparts some variation in the operation of the individual circuit elements as well as larger circuit structures within a given integrated circuit. For example, if the fabrication of a given complementary-symmetry metal-oxide semiconductor (CMOS) wafer results in highly resistive (“slow”) p-channel field-effect transistors (P-FETs), then circuits that incorporate P-FETs will tend to be characterized by slow positive-going voltage slew rates relative to circuits fabricated on wafers that include highly conductive (“fast”) P-FETs. Process variation in n-channel field-effect transistors (N-FETs) has a similar effect in pull-down performance.
Certain types of CMOS circuits, such as conventional combinational logic gate circuits, tend to be highly robust in maintaining correct function when subjected to process variation. For example, many static logic gate circuits produce correct output values over a very wide range of process variation, with only the input to output propagation delays and output slew rates being significantly impacted by process variation. However, many types of specialty circuits commonly used in CMOS integrated circuits generally require relatively well bounded process variation to function correctly. These specialty circuits offer a very efficient implementation of a specific building block function, but certain classes of these specialty circuits malfunction catastrophically with sufficient process variation.
One type of specialty circuit is a flop-flop (or just “flop”) based on a differential sense amplifier structure. Conventional sense amplifier flop designs offer certain benefits over alternative design regimes. However, the differential structure commonly employed in the sense amplifier flop design is typically sensitive to process variation. In fact, conventional sense amplifier flop designs are prone to malfunctions due to process variation. Specifically, these differential structures require a bounded conductivity ratio between N-FETs and P-FETs within a given integrated circuit. This conductivity ratio is dictated by the process outcome for a given wafer. When the process outcome for a given wafer produces a conductivity ratio that is out of bounds for at least one sense amplifier flop within an integrated circuit on the wafer, all integrated circuits fabricated on the wafer are likely to malfunction and fail manufacturing tests, resulting in a complete loss the wafer. When a set of different integrated circuits incorporates a sense amplifier flop design that may be highly sensitive to process variation, every instance of the sense amplifier flop in every different integrated circuit design may be highly susceptible to failure, resulting in a costly overall loss of yield over many different designs and many different wafers.
One approach to improve sense amplifier flop reliability is to tighten process variation requirements on host wafers. However, such an approach tends to involve significant expense in the fabrication process and inherent yield loss during wafer sorting and qualification testing.
As the foregoing illustrates, what is needed in the art is a high-performance sense amplifier flop design that is substantially insensitive to process variation.